The present invention relates to a semiconductor memory device, and in particular, to methods of using and designing a dynamic random access memory (DRAM) device.
As well known, DRAM devices are one of the dominant memory devices and, due to their high density and relatively low manufacturing cost, are presently used for the majority of memory applications. For example, DRAM devices are used as main memories in computer systems, graphic memories on graphic cards, buffer memories on network cards, or the like.
With more recent microprocessors operating at 1 GHz and above, DRAM devices are also required to operate at a faster rate. To obtain the high-rate operation, especially to shorten command intervals in DRAM device, one of relevant approaches known to the inventors divides common I/O lines into more common I/O lines, according to the division of the memory cell arrays. The relevant approach decreases the xe2x80x9cRxe2x80x9d component of time constant xe2x80x9cCRxe2x80x9d in relation to each of common I/O lines, so as to obtain the high-rate operation.
The above relevant approach, however, causes chip-size of DRAM device to be large. According to the relevant approach, the length of each of the common I/O lines becomes short to make the xe2x80x9cRxe2x80x9d component small, while the number of the common I/O lines increases. Because the common I/O lines are coupled to the respective column-related circuits, such as write amplifiers, read amplifiers and precharge circuits, the relevant approach requires more column-related circuits, as the number of the common I/O lines increases. Thus the number of column-related circuits also increase requiring larger physical space.
In addition, the above relevant approach does not consider characteristics of xe2x80x9cmemory applications.xe2x80x9d Data read/write operations are not the same in memory applications, and data sequences are handled in various manners. In spite, the above relevant approach is not an application-specified approach, but an approach common to all memory applications. Therefore, the relevant approach might not be feasible for some memory applications.
Thus, it is desirable to provide faster DRAM devices, in particular, ones that are small in chip-size.
The present invention provides a DRAM device which is feasible for at least some memory applications and which can achieve high-rate operation.
In some of memory applications, such as a graphic memory on a graphic card or a buffer memory on a network card, data are sequentially written into a memory device and are also sequentially read out of the memory device. In this case, memory controller for the memory device can consciously select, for each predetermined data length, different one of memory banks included in the memory device, and thereby, can easily predict the memory bank sought to be written data into or sought to be read data out.
The inventors of the present invention direct their attention to the characteristics of the data read/write operations in some memory applications, then define two types of command interval specifications. According to one aspect of the present invention, one of the command interval specifications is defined as the relationship between a preceding command and a following command that are issued for the same bank, while the other of the command interval specifications is defined as the relationship between a preceding command and a following command that are issued for different banks, respectively. The former is referred to as a first command interval specification, while the latter is referred to as a second command interval specification. The first and second command interval specifications are different from each other. As for the second command interval specification, since target banks are different between a preceding command and a following command, the following command can be executed during the column circuits precharge (e.g. a precharge of a common I/O line) after the preceding command. Therefore, a time interval defined in the second command interval specification can be shorter than another time interval defined in the first command interval specification, in accordance with some commands, such as commands accompanied with the column circuits precharge.
One aspect of the present invention further defines pairs of banks as bank pairs, and furthermore, applies the first and second command interval specifications to the bank pairs. That is, in the bank pair case, the first command interval specifications is defined as the relationship between a preceding command and a following command that are issued for the same bank pair, while the second command interval specifications is defined as the relationship between a preceding command and a following command that are issued for different bank pairs, respectively.
In addition, because the memory controller can easily control the data allocation in accordance with some applications, the memory controller can easily lower the probability that the first command interval specification. This allows the banks belonging to the same bank pair to share the respective column-related circuits, and makes the memory speed high, because the probability that the second command interval specification is used is higher. Thus one aspect of the present invention provides a DRAM that is small in chip-size because of the sharing the column-related circuits and that is faster for some memory applications.
It is to be understood that both the foregoing description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.